This application relates to a semiconductor device, specifically, a semiconductor transistor device suitable for analog and digital circuits.
For more than 30 years, the integrated circuit industry has followed a dramatic path of shrinking device dimensions and increasing chip sizes, resulting in steadily increased performance and increased functionality. New generations of devices have appeared in every two to three years, following the so called xe2x80x9cMoore""s Lawxe2x80x9d, with each new generation device approximately doubling logic circuit density, increasing performance by about 40%, and quadrupling the memory capacity comparing to the previous generation. The consistency of this advancement has led to an expectation that faster and more powerful chips will continue to be introduced on the same schedule in the foreseeable future.
The silicon semiconductor industry has charted a course for itself over the next 15 years, which attempts to continue the density and performance improvements of the past 40 years. The International Technology Roadmap for Semiconductor (ITRS) has forecasted that this device scaling and increased functionality scenario to continue until 2013, at which point the minimum feature size is projected to reach 32 nm and a single chip is expected to contain more than 1011 components.
Most of the historic trend has been achieved with the same basic switching element (the MOS transistor) and the same basic circuit topology (CMOS) based on a limited number of materials (Si, SiO2, Al, Si3N4, TiSi2, TiN, W, primarily). While very substantial human and financial resources invested have improved manufacturing practices over the past 40 years, the device structures of 30-40 years ago are still quite recognizable in today""s IC industry.
A large part of the success of the MOS transistor is due to the fact that it can be scaled to increasingly smaller dimensions, which results in higher performance. The ability to improve performance consistently while decreasing power consumption has made CMOS architecture the dominant technology for integrated circuits. The scaling of the CMOS transistor has been the primary factor driving improvements in microprocessor performance. The transistor delay has decreased by more than 30% per technology generation resulting in a doubling of microprocessor performance every two years. In order to maintain this rapid rate of improvement, aggressive engineering of the MOS transistor is required.
Conventional scaling of gate oxide thickness, source/drain extension (SDE) junction depths, and the gate lengths has enabled MOS gate dimensions to be reduced from 10 xcexcm in the 1970""s to a present day size of 0.1 xcexcm. To enable transistor scaling into the 21st century, new solutions such as high dielectric constant materials for gate insulation and shallow junctions with low resistivity need to be developed.
Silicon technology has reached the point at which significant innovations will be required to circumvent the challenges associated with continued MOSFET scaling. Current performance scaling trends will not continue past the 0.1 xcexcm device technologies by using traditional scaling methods. Fundamental limits in SiO2 scaling due to tunneling current, in SDE junction depths due to large increases in external resistance, and in well engineering due to leakage constraints are currently being reached. The most apparent challenges are gate insulators with high dielectric constant and ultra-shallow junctions with low sheet resistance. At present, there are no known solutions for the MOS device technologies to continue the performance trends seen in the last 20 years. Practical and fundamental limits are being approached and substantial changes to device technologies and structures are required.
Aggressive scaling of silicon integrated devices in the deep sub-micron range presents considerable challenges to device engineers. Device performance must be preserved as much as possible, when going from one generation to the next, while the devices must be manufacturable and cost-effective. As the milestone of 32-nm gate length MOSFET is approached, alternative device structures are being considered that might allow the continuation of scaling trends when physical limits of conventional MOSFETs are eventually reached. There is therefore a need to provide a device structure to enable the continued downward scaling of transistor dimensions into the 21st century.
Implementations of the system may include one or more of the following. The invention system generally includes a three-terminal semiconductor transistor device, comprising:
a) a base region formed by a semiconductor material, the base region being in contact with a first electric terminal;
b) a conductive emitter region in contact with the semiconductor base region, forming a first Schottky barrier junction at the interface of the conductive emitter region and the semiconductor base region, the conductive emitter region being in contact with a second electric terminal; and
c) a conductive collector region in contact with the semiconductor base region, forming a second Schottky barrier junction at the interface of the conductive collector region and the semiconductor base region, the conductive collector region being in contact with a third electric terminal,
wherein the tunneling current through the first Schottky barrier junction or the second Schottky barrier junction is substantially controlled by the voltage of the semiconductor base region.
In another aspect, the invention system includes a three-dimensional three-terminal semiconductor device, comprising:
a) a first insulating substrate layer; and
b) a second substrate layer formed above the first insulating substrate layer, comprising
i) a base region formed by a semiconductor material, the base region being in contact with a first electric terminal;
ii) a conductive emitter region in contact with the semiconductor base region, forming a first Schottky barrier junction at the interface of the conductive emitter region and the semiconductor base region, the conductive emitter region being in contact with a second electric terminal; and
iii) a conductive collector region in contact with the semiconductor base region, forming a second Schottky barrier junction at the interface of the conductive collector region and the semiconductor base region, the conductive collector region being in contact with a third electric terminal,
wherein the tunneling current through the first Schottky barrier junction or the second Schottky barrier junction is substantially controlled by the voltage of the semiconductor base region.
In still another aspect, the invention system includes a three-dimensional three-terminal semiconductor device, comprising:
a) a first electric terminal formed in a lower substrate layer;
b) a middle substrate layer, comprising
i) a lower conductive region in contact with the first electric terminal in the lower substrate layer,
ii) a middle semiconductor region in contact with the lower conductive region in the lower substrate layer forming a first Schottky barrier junction at the interface of the middle semiconductor region and the lower conductive region, such middle semiconductor region being in contact with a second electric terminal; and
iii) an upper conductive region in contact with the middle semiconductor region forming a second Schottky barrier junction at the interface of the upper conductive region and the middle semiconductor region, such upper conductive region being separated from the lower conductive region by the middle semiconductor region; and
c) a third electric terminal formed over the middle substrate layer, the third electric terminal being in contact with the upper conductive region in the middle substrate layer,
wherein the tunneling current through the first Schottky barrier junction or the second Schottky barrier junction is substantially controlled by the voltage of the middle semiconductor region.
The new device structure described in the present invention is called Schottky Barrier Tunneling Transistor (SBTT). The basic device structure is a metal-semiconductor-metal (MSM) sandwich structure. This structure has two Schottky diodes connected back-to-back. The SBTT transistor has three terminalsxe2x80x94emitter, base, and collector. The emitter and the collector regions are made of metals or silicides. The base region is made of a semiconductor such as silicon. The device has two complimentary device typesxe2x80x94n-channel and p-channel transistors. The base is n-type doped for an n-channel SBTT and p-type doped for a p-channel SBTT. The emitter-to-base junction and the collector-to-base junction are Schottky barrier junctions. The device is normally off because carriers are blocked by the two Schottky barriers.
The current conduction mechanism in SBTT is primarily attributed to the tunneling current through the emitter-base and collector-base Schottky barriers. The Schottky barrier widths and heights are modulated by the base voltage. When the base of an n-channel SBTT is positively biased, the Schottky barrier widths and heights are reduced, and electrons can tunnel through the Schottky barriers. If the collector is also positively biased, the injected electrons can transport through the thin base region without recombinations because electrons are the majority carriers in the n-type doped base. For a p-channel SBTT, the base is negatively biased to turn on the device.
The SBTT is a symmetric device when the emitter and the collector are made of the same material. The emitter and the collector are then interchangeable in the circuit design. The emitter and the collector can even be made of the same material for both n- and p-channel SBTTs. The device parameters, such as the base width, the base doping density, and the potential barrier heights for electrons and holes, can be properly chosen to produce symmetric Ixe2x88x92V characteristics for n- and p-channel devices. For example, if the emitter/collector metal (or silicide) work function is slightly below the mid band gap of the base semiconductor, the potential barrier height for holes is smaller than the potential barrier height for electrons. The asymmetric potential barriers can compensate the higher tunneling efficiency of electrons than that of holes because electrons have a higher effective Richardson constant and a smaller effective mass than those of holes. In the digital circuit design using SBTTs, on the same current path, the transistor sizes of n- and p-channel devices can be the same to create a compact layout design. On the other hand, in the CMOS digital circuit design, the p-channel MOSFET usually needs to be three times bigger than the n-channel MOSFET to achieve the same driving current because the electron mobility is about three times of the hole mobility. The unequal transistor sizes between n- and p-channel MOSFETs will increase the chip size and reduce the utilization efficiency on the silicon area.
The SBTT provides complete solutions for the issues with the MOS device scaling. The SBTT has better scalability than the MOSFET because of its compact geometries and structural simplicity. There are currently no known solutions for the three major challenges for the MOS device scaling, namely, the gate insulators with high dielectric constant, the source/drain shallow junctions with low sheet resistance, and the low power supply voltage. In contrast, the SBTT does not have the gate insulator issue because it is not a field effect transistor and thus does not need a gate insulator.
The emitter and the collector of a SBTT are made of low-resistance metals or silicides, which significantly reduce the emitter/collector series resistances and increase the device driving current. The SBTT is promised to be a high-speed device because of its thin base and low emitter/collector series resistances. For a MOS device, the source and drain are heavily doped semiconductors. The source/drain series resistances and the contact resistances are increased with device scaling because the contact sizes and the source/drain junction depths become smaller. The increasing parasitic resistances substantially degrade the driving current of nano-scale MOSFETs. Although the MOS device speed is improved by scaling the gate length, the delay from the parasitic resistances plays an increasingly important role. For a SBTT, the contacts between interconnect lines and the emitter/collector regions are metal-to-metal or metal-to-silicide contacts. The contact resistances are negligible compared to the contact resistances of the source/drain metal-to-semiconductor contacts.
Another advantage of the present invention is that the invention SBTT device can be operated at a low power supply voltage due to its unique current conduction mechanism. The SBTT device can operate, for example, 0.4 V or below, because the current conduction mechanism is quantum mechanical tunneling. The electrons inject from the conduction band of the emitter to the conduction band of the base through the emitter-base Schottky barrier by tunneling. The power supply voltage does not need to be large enough to induce the carrier inversion. The device can be designed so that the Schottky barrier can be modulated by a small base voltage. The device simulation shows that the turn-on behavior of a SBTT is more sensitive than that of a MOSFET. On the other hand, the current conduction mechanisms are drift and diffusion in a MOSFET. For an n-channel MOSFET, the silicon surface needs to be inverted from p-type to n-type by a positive gate voltage and forms a channel to connect the source and the drain. The required gate voltage depends on the gate insulator thickness, gate insulator dielectric constant, surface doping, and the silicon band gap. The surface doping actually increases with shrinking device dimensions in order to suppress the short channel effect. The reduction of power supply voltage in the past is primarily attributed to the gate oxide thickness reduction. To have a reasonable on/off current ratio, the power supply voltage is difficult to be smaller than 0.6 V. In the last 10 years, the MOS device scaling basically follows the constant electric field scaling rules to maintain constant electric fields inside the device. For example, the average electric field between drain and source remains the same when the technology migrates from 0.5 xcexcm (with Vdd=5 V) in 1993 to 0.1 xcexcm (with Vdd=1 V) in 2003. In the next 10 years, according to the ITRS Roadmap, the scaling of power supply voltage is slower than the scaling of MOS device geometries. For example, the power supply voltage is only reduced to 0.6 V for the 32-nm technology in 2013, which should be 0.32 V if the constant electric field scaling rules are strictly followed. The maximum electric fields in the gate insulator and in the channel will be increased for the future small geometry devices. The higher electric fields will cause the problems of higher gate leakage current, short channel effect, hot-carrier injection, gate insulator reliability, and higher power consumption. The difficulty of scaling down the power supply voltage should eventually slow down the MOS device scaling roadmap.
Yet another advantage of the present invention is that the SBTT chip will consumes less power than a comparable CMOS chip. Since the power supply voltage can be reduced with the shrinking device dimensions, the SBTT can follow the constant electric field scaling rules. The power density per unit area can he maintained as a constant for different technology generations. In contrast, the power density of a CMOS chip will be increased because the power supply voltage is higher than the value suggested by the constant electric field scaling rules. Moreover, the SBTT""s emitter/collector series resistances are significantly smaller than MOSFET""s source/drain series resistances. The SBTT""s emitter/collector metal-to-metal contact resistance is also significantly smaller than MOSFET""s metal-to-semiconductor contact resistance. The power consumption due to the parasitic components of SBTTs is much smaller than that of MOSFETs.
Still another advantage of the invention is that SBTT overcomes many of the difficulties in the fabrication of the nano-scale MOS devices. The SBTT structure requires no source/drain junctions. This property alleviates the requirement of very steep p-n and n-p junctions and extremely high doping in source/drain regions, which are significant challenges in the fabrication of small-geometry MOSFETs. The SBTT structure also requires no gate insulator. This property alleviates the requirement of a thin gate insulator with a high dielectric constant, low gate leakage, and low interface state density. The SBTT fabrication process is compatible with conventional silicon CMOS technologies. The SBTT process is simpler and costs less than a CMOS process because the SBTT process requires less photo masking steps than a CMOS process. The emitter and the collector can be made of the same metal or silicide material for both n- and p-channel SBTTs, while MOSFETs require separate implantations and photo masking steps for the n+ S/D junctions of n-channel MOSFETs and the p+ S/D junctions of p-channel MOSFETs. The metals and silicides, such as Ti, Ta, Co, Ni, W, WSi2, CoSi2, NiSi2, TiSi2, TaSi2, and MoSi2, are commonly used in the silicon CMOS technologies. The material properties of the above metals and silicides are well known. The process equipment and the process technologies are readily available. Two manufacturing processes are described below to fabricate horizontal and vertical SBTTs using the technologies compatible with the conventional silicon CMOS technologies.
Another advantage of the invention is that a SBTT is smaller than a MOSFET, allowing more SBTTs to be packed on the same chip area than MOSFETs. The MOSFET is a four-terminal device, which requires a substrate contact to provide the body bias. The SBTT is a three-terminal device and does not need the substrate contact. The substrate contacts for CMOS devices are sometimes called well taps because n-channel MOSFETs are usually built in p-wells and p-channel MOSFETs are usually built in n-wells. The p-well is normally tied to the ground and the n-well is normally tied to Vdd. Although the well tap is not required for every single transistor, however, from the latch-up concern, the well taps are preferably to be placed as close to the device as possible. The source/drain contacts of a MOSFET are metal-to-semiconductor contacts. The contact resistance increases with shrinking the contact size. Typically, it is recommended to put as many source/drain contacts as possible to reduce the total contact resistance. The emitter and the collector of a SBTT are made of metals or silicides, the contact resistances between interconnect lines and the emitter/collector regions are negligible. That means the number of emitter/collector contacts of a SBTT can be smaller than the number of source/drain contacts of a MOSFET. The conductive materials for the SBTT""s emitter/collector regions can also be used as local interconnects to connect adjacent devices. The local interconnects provide an additional degree of design freedom at no additional cost. In the silicon CMOS technologies, the following materials, such as TiN, TiSi2, polysilicon, and polycide, have been used as local interconnects, however, at the cost of one additional photo mask.
The invention SBTT devices provide Ixe2x88x92V characteristics similar to MOSFETs and bipolar transistors. The SBTT devices can be used in both digital and analog circuit designs. For digital applications, all people need is a three-terminal switch where the conductance between two terminals is strongly controlled by the third. For the MOS device, the drain-to-source conductance is controlled by the gate voltage. For the bipolar transistor and SBTT, the collector-to-emitter conductance is controlled by the base voltage. The device simulation shows that the turn-on behavior of a SBTT is strongly dependent on the base voltage, which indicates the SBTT is suitable for low-power and high-speed applications. The analog design using SBTT devices resembles the traditional analog design using bipolar transistors because both devices have exponential relationships between the collector current and the base voltage.
The details of one or more embodiments are set forth in the accompanying drawing and in the description below. Other features, objects, and advantages of the invention will become apparent from the description and drawings, and from the claims.